Memory is used for storage of data and/or program code in many electronic products, such as personal computer systems, embedded processor-based systems, video image processing circuits, portable phones, and the like. Memory cells may be provided in the form of a dedicated memory integrated circuit (IC) or may be included within a processor or other IC as on-chip memory. Ferroelectric memory, sometimes referred to as “FRAM” or “FERAM”, is a non-volatile form of memory commonly organized in single-transistor, single-capacitor (1T1C) or two-transistor, two-capacitor (2T2C) configurations, in which each memory cell includes one or more access transistors. The cells are typically organized in an array, and are selected by plateline and wordline signals from address decoder circuitry, with the data being read from or written to the cells along bitlines using sense amp circuits.
Continuing design efforts are directed toward increasing memory density in semiconductor products, by decreasing the size of the cells. In constructing ferroelectric memory cells, the plateline and wordline signals, as well as the bitlines need to be routed to the appropriate terminals of the cell transistor and capacitor. In a 1T-1C cell, the ferroelectric capacitor is connected between a source/drain of the cell transistor and the plateline signal. The other transistor source/drain is connected to a bitline and the gate is connected to the wordline signal. The configuration of the cell components and interconnect routing structures plays a role in reducing the cell size in an array.
One layout architecture is referred to as ‘capacitor under bitline’, wherein the bitline is routed in an interconnect layer above the level at which the ferroelectric capacitor is formed. The capacitor under bitline architecture is preferred for many high-density memories, including embedded memories. For embedded memories, FRAM processing is performed following standard logic front end processing (e.g., after contact formation in an initial interlevel or interlayer dielectric layer (ILD0)) and before back end processing (e.g., prior to fabrication of metal interconnect layers). In the capacitor under bitline configuration, area must be dedicated to routing the bitline connection from the underlying transistor source/drain to the interconnect layer at which the bitline routing structures are created. This requires a bitline contact/via structure which passes through the ferroelectric capacitor level. For planar ferroelectric memory cells of small dimensions (e.g., areas below about 0.25 um2), the size of the ferroelectric capacitor begins to control the cell size. Consequently, reducing the cell area is facilitated by maximizing the ferroelectric capacitor area.
A portion of a conventional open-bit ferroelectric memory array cell layout is illustrated in a device 2 in FIGS. 1A-1D. FIG. 1A provides a sectional side view of the device 2 taken along lines 1A—1A in FIGS. 1B-1D, which provide sectional top views of the device 2 along lines 1B—1B, 1C—1C, and 1D—1D, respectively, of FIG. 1A. The device 2 includes a silicon substrate 4 in which transistor source/drains 6 and isolation structures 8 are formed, and polysilicon gate structures 10 formed over channel regions of the substrate 4. MOS type cell transistors are thus formed by the gates 10 and the source/drains 6, wherein the source/drains 6 are formed by doping portions of active regions 12 in the substrate (FIG. 1B), and wherein some of the source/drains 6 are shared between adjacent transistors. A first interlevel or interlayer dielectric (ILD) layer 14 is formed over the transistors and the substrate 4, through which conductive contacts 16 are formed. Ferroelectric capacitors C are formed over the dielectric layer 14, including upper and lower electrodes or plates 18 and an interlying ferroelectric material 20.
As seen in FIGS. 1A and 1C, a second dielectric layer 22 overlies the capacitors C and the first dielectric 14, and conductive via structures 24 are formed therethrough to couple the upper capacitor plates 18 and the contacts 16 of the first layer. A third dielectric layer 26 is formed over the preceding dielectric 22, and a first layer of metal interconnect structures (M1) are formed therein, including conductive plateline routing structures 28 and landing pads 30 for the bitline connections. Bitline connection vias 32 are formed through the dielectric 26 to connect the landing pads 30 with a bitline structure 34 in a second metalization layer M2 in a succeeding ILD layer 36. As seen in FIG. 1C, there is a minimum distance 38 between the capacitor C and the bitline via 24 at the capacitor level in the ILD layer 22. While the conventional cell layout in the device 2 is simple for the transistors (e.g., straight gate structures 10, rectangular active regions 12), the capacitor efficiency or space utilization is limited because of all of the empty space required to place the bitline vias 24 between capacitors C. As the semiconductor industry continues the trend toward providing higher and higher memory densities, there remains a need for improved ferroelectric memory cells and methods for fabricating ferroelectric memory by which capacitor space utilization efficiency can be increased.